The next generation of high-speed communication systems and the power electronics required for cutting-edge data centres are expected to rely heavily on gallium nitride, a sophisticated semiconductor material.
Sadly, the use of gallium nitride (GaN) in commercial applications has been restricted due to its expensive cost and the level of expertise needed to integrate this semiconductor material into traditional circuits.
In order to combine high-performance GaN transistors onto conventional silicon CMOS devices in a method that is affordable, scalable, and compatible with current semiconductor foundries, researchers from MIT and other institutions have now created a novel fabrication technique.
Using a low-temperature procedure that maintains the functioning of both materials, their technique entails creating a large number of tiny transistors on the surface of a GaN chip, cutting off each individual transistor, and then glueing just the required number of transistors onto a silicon chip.
Compact, high-speed transistors can significantly improve the device’s performance, but the cost is kept low because just a little amount of GaN material is added to the chip. Furthermore, the new approach lowers the system’s total temperature by breaking the GaN circuit up into individual transistors that can be dispersed throughout the silicon chip.
Using this method, the researchers created a power amplifier—a crucial part of cell phones—that outperforms silicon transistor-based devices in terms of signal strength and efficiency. This could increase wireless bandwidth, improve connectivity, prolong battery life, and improve call quality in a smartphone.
Their approach could enhance current electronics as well as upcoming technology because it conforms to conventional methods. Since GaN outperforms silicon at the cryogenic temperatures required for many forms of quantum computing, the novel integration approach may eventually even allow for quantum applications.
It is obvious that we should use this technology if we can lower the cost, increase scalability, and simultaneously improve the performance of the electronic gadget. We have integrated the greatest available gallium nitride electronics with the best silicon technology.
The principal author of a publication on this technique and graduate student at MIT, Pradyot Yadav, claims that “these hybrid chips can revolutionise many commercial markets.” The research was presented at the Radio Frequency Integrated Circuits Symposium (RFIC 2025) RTu2C session, which took place in San Francisco, California, during June 15–17, 2025.
Swapping transistors
Just after silicon, gallium nitride is the second most used semiconductor worldwide. Because of its special qualities, it is perfect for uses including power electronics, radar systems, and lighting.
The material has been around for decades, and GaN devices must be coupled to silicon digital chips, also known as CMOS chips, in order to achieve their optimum performance. Some integration techniques use soldering to bond GaN transistors onto a CMOS chip in order to make this possible, but this restricts the size of the GaN transistors. The frequency at which transistors can function increases with their size.
There are other ways to integrate a whole gallium nitride wafer on top of a silicon wafer, but it is very expensive to use so much material, especially when only a small number of tiny transistors require GaN. The GaN wafer’s remaining material is squandered.
“We aimed to integrate the capabilities of GaN with the strength of silicon-based digital circuits without sacrificing either bandwidth“. Yadav says, “We did that by putting incredibly tiny discrete gallium nitride transistors directly on top of the silicon chip.”
A multi-step process produced the new chips.
Initially, the whole surface of a GaN wafer is covered with a densely packed array of tiny transistors. They create what they refer to as a dielet by using extremely precise laser technology to trim each one down to just the transistor’s size, which is 240 by 410 microns. (One millionth of a metre is called a micron.)
They employ the tiny copper pillars that are produced on top of each transistor to bond directly to the copper pillars on the surface of a typical silicon CMOS chip. Below 400 degrees Celsius, copper can be bonded to copper at temperatures low enough to prevent damage to both materials.
Gold, a costly material that requires significantly higher temperatures and stronger bonding strengths than copper, is needed for the bonds used in current GaN integration procedures. Gold usually requires specialised facilities since it can contaminate the tools used in the majority of semiconductor foundries.
“We sought a low-temperature, low-force, and low-cost technique, and copper outperforms all of those associated with gold“. In addition, it has superior conductivity, according to Yadav.
A new tool
They developed a specialised new instrument that can precisely integrate the minuscule GaN transistor with the silicon chips in order to facilitate the integration procedure. The device zeroes in on the copper bonding contact with nanometre accuracy by using a vacuum to retain the dielet while it moves on top of a silicon chip.
After monitoring the interface using sophisticated microscopy, they bonded the GaN transistor to the chip by applying pressure and heat once the dielet was in the proper place.
“I had to locate a new collaborator who was proficient in the approach I needed for each step of the process, pick their brain, and then incorporate that into my platform“. Yadav says, “It was two years of continuous learning”.
The researchers proved their fabrication technique by creating power amplifiers, which are radio frequency circuits that enhance wireless transmissions, after they had mastered it.
Their devices outperformed those using conventional silicon transistors in terms of gain and bandwidth. The area of each tiny chip is less than half a square millimetre.
Additionally, they were able to include components frequently seen in silicon circuits, including neutralisation capacitors, because the silicon chip they utilised in their demonstration is based on Intel 16 22nm FinFET state-of-the-art metallisation and passive choices. This brought the amplifier one step closer to enabling the upcoming wireless technologies by greatly increasing its gain.
Heterogeneous integration has become a viable way to continue system expansion, lower form factor, increase power efficiency, and optimise cost in order to counteract Moore’s Law’s slowdown in transistor scaling.
The realisation of unified systems comprising front-end integrated circuits, baseband processors, accelerators, and memory for next-generation antennas-to-AI platforms, particularly in wireless technology, depends on the close integration of compound semiconductors with silicon-based wafers.
“This work pushes the boundaries of current technological capabilities and makes a significant advancement by demonstrating 3D integration of multiple GaN chips with silicon CMOS,” says Atom Watanabe, an IBM research scientist who was not involved with this paper.
